Design Verification Engineer

We are seeking a Design Verification Engineer experienced in building UVM-based verification environments and verification models. The candidate will define verification plans, implement UVM testbenches and VIPs, collect function and code coverage, analyze uncovered points, and drive closure to ensure high-quality RTL sign-off.

Key Responsibilities

1. Plan and build UVM-based DV environments for complex SoC/IP verification.
2. Architect and implement verification models (behavioral/instructional models, transaction-level models, protocol models) required for thorough validation.
3. Define comprehensive Verification Plans that map requirements to testbench strategies and coverage goals.
4. Develop and integrate required VIPs (Verification IP) and reusable test components into the UVM environment.
5. Implement directed and constrained-random tests, scoreboards, monitors, and assertions to validate functionality and check protocol compliance.
6. Collect, monitor, and report Functional Coverage and Code Coverage metrics; identify coverage holes and drive closure through targeted tests and environment enhancements.
7. Use SVA (SystemVerilog Assertions) to specify and check properties; maintain assertion libraries.
8. Collaborate closely with RTL designers, DV team members, system architects, and software/bring-up teams to debug issues and perform root-cause analysis.
9. Automate regression flows, tool runs, and coverage collection; maintain CI/regression infrastructure.
10. Document verification results, create test plans/reports, and present findings in design and verification reviews.

Requirements:

• Master's degree or Ph.D. in Electrical Engineering, Computer Engineering, or related fields.
• Minimum 35 years experience in DV/verification
• Proven experience planning and building UVM verification environments.
• Proven experience planning and building verification models.
• Strong proficiency in SystemVerilog and Verilog.
• Strong proficiency in UVM methodology and testbench architecture.
• Experience with SystemVerilog Assertions (SVA) design and verification.
• Proficient in programming/scripting: C++, Python, and Perl.
• Experience collecting and analyzing Functional Coverage and Code Coverage; driving coverage closure.
• Solid debugging skills with waveform viewers and simulator flows (e.g., QuestaSim, VCS, Xcelium).