< div> (1) Graduated with a master's degree or above in electrical engineering and information related departments.
(2) Familiar with Verilog RTL, Synthesis, Simulation, Timing Analysis and other related IC Design Flow.
(3) Familiar with Design for Testability technology, including Scan / ATPG, Delay Test, Memory BIST, Boundary Scan, Diagnosis, etc.
(4) Experience in using DFT Tools (such as DFT Compiler, TetraMAX, BSD Compiler, FastScan, TestKompress, MBISTArchitect) is preferred.
(5) Actively responsible, brave to meet challenges, interested in Nanometer / SoC DFT Implementation, development and promotion design process.
(MD1430002)
