Responsibilities
1. Work with cross-functional teams to analyze MR product SOC architecture requirements, and define chip external interfaces, custom IP, memory bandwidth, interconnection protocols, power and other related requirements 2. Based on MR product system functions and usage scenarios, define the SOC internal data path control process and related modes 3. Define the internal software and hardware division of the chip, drive efficient system software and hardware architecture, and collaboratively optimize to meet product needs 4. Responsible for power consumption and performance analysis, weighing the trade-offs in the SOC design process, and exploring innovative and efficient architectural solutions to achieve product requirements 5. Promote the chip design team or chip design supplier to meet SOC requirements.
Qualifications
1. Master degree or above, majoring in microelectronics, electrical engineering, computer science 2. Have experience in SOC architecture design, understand the trade-off of performance, power consumption and area in the SOC design process 3. Familiar with chip interfaces and related protocols, storage systems, inter-core communication, hardware/software division experience 4. Familiar with advanced process manufacturing, low-power digital circuit design and verification process methods 5. Familiar with SOC system status, memory bandwidth and power consumption analysis 6. Open-minded, passionate about new technologies, with excellent communication and writing skills. Bonus points: 1. Experience in image, display or AI acceleration subsystems (including ISP, DPU, NPU and their micro-architecture) 2. Experience in FPGA programming and IP prototyping 3. Strong programming skills and familiarity with C/C++ 4. Project experience in low-power consumer electronics design.
