Chip Integration/STA Engineer (Shanghai)

1. Responsible for logic synthesis, formal verification, STA Signoff and other tasks in the SoC chip 2. Cooperate with other teams to complete the Clock/Reset solution, Low Power solution, timing closure and other tasks in the chip design process 3. Be familiar with SDC and various timing checks, and become the timing gatekeeper before tape-out.

1. Master's degree or above, graduated in microelectronics/electronics/computer and other related majors, more than 2 years of relevant work experience 2. Possess proficient scripting skills (such as TCL, Perl, Python, etc.) 3. Proficient in using EDA tools such as DC/PT/Formality/LEC/Tempus, and master the methodology of logic synthesis and STA 4. Candidates familiar with SoC DFT are preferred 5. Good teamwork spirit and serious and responsible work attitude 6. Good communication skills and smooth English reading and writing.