ASIC verification engineer (RDMA direction)

1. Responsible for module-level or system-level verification of chips, and complete the formulation and execution of verification plans in accordance with process quality requirements 2. Responsible for test point decomposition and use case design, reusable verification environment construction, test case execution, problem ticket recording and analysis, and coverage collection and analysis 3. Responsible for maintaining the verification environment, completing problem regression and coverage convergence, and writing verification reports 4. Assisting designers with debug and performance analysis, or system-level verifiers to integrate the verification environment.

1. Bachelor degree or above in microelectronics, computer and other related majors, with independent module-level verification experience, tape-out experience is preferred 2. Familiar with the chip verification process, proficient in verification-related EDA tools, and proficient in mainstream verification methodologies such as UVM 3. Proficient in SystemVerilog language, familiar with one or more of the C/C++/SystemC modeling languages, and familiar with Python/Makefile scripting language 4. Familiar with the RDMA protocol and have experience in verifying related functions. Bonus points: 1. Experience in large-scale network simulation modeling, familiar with congestion control 2. Familiar with RDMA kernel mode user mode driver 3. Familiar with collective communication software.