We are seeking a highly skilled IC Layout Engineer to join our team to develop LCoS (Liquid Crystal on Silicon) display ASICs. You will be responsible for full‑custom digital and analog layout optimized for electro‑optical performance, yield, reliability, and manufacturability in CMOS processes.
You will work closely with analog and digital design engineers in chip floorplan, power and signal routing, and post layout simulation. You will also lead final sign-off task.
What You Will Do (Key Responsibilities)
- Physical Layout Implementation
- Perform detailed block‑level and/or full‑chip layout for advanced ASIC designs
- Translate schematics and RTL intent into high‑quality physical layouts
- Optimize layout for PPA (power, performance, area)
- Floorplan & Power Grid Support
- Contribute to block and chip‑level floor planning
- Implement and refine power grids (PDN) including rings, straps, and local grids
- Support multi‑power‑domain designs and isolation strategies
- Physical Verification & Signoff
- Own and close:
- DRC, LVS, ERC,
- Density, antenna, and reliability checks
- Debug complex physical verification issues independently
- Support final tape‑out signoff
- Performance & Reliability Optimization
- Minimize parasitic RC and coupling noise
- Address IR drop, EM, and self‑heating concerns
- Insert and optimize decoupling capacitors
- Support post‑layout extraction (PEX) and timing/power analysis
- Cross‑Functional Collaboration
- Work closely with circuit designers, RTL and physical design teams, foundry, and process engineers
- Provide early feedback on layout feasibility and risks
- Methodology & Quality Improvement
- Apply and help refine layout best practices
- Improve layout reusability, efficiency, and robustness
- Support PDK updates and technology migrations
Required
Who You Are (Basic Qualifications)
- BS/MS/Ph.D. in Electrical Engineering or related field.
- 3–10+ years of experience in ASIC layout.
- Strong proficiency with
- Cadence Virtuoso (layout + Pcells + Innovus +SKILL automation preferred)
- PVS or Calibre for DRC/LVS/PEX
- Solid understanding of
- Analog layout matching
- Signal integrity, parasitic, IR drop, shielding
- Multi‑metal routing, density rules, guard‑ring/ESD practices
- Experience closing complex designs to manufacturing sign‑off
Preferred
- Experience with display driver ICs, LCOS, DLP, TFT‑LCD, or image sensor layout
- Hands‑on experience with multi‑VDD designs
- Familiarity with:
- Tower, GlobalFoundries, TSMC, or UMC CMOS processes
- High‑precision MIM capacitor layout
- Pixel array tiling and stitching
- Ability to lead complex blocks with minimal supervision
What Will Put You Ahead (Soft Skills)
- Strong communication and teamwork.
- Ability to manage multiple blocks and deadlines.
- Detail‑oriented with excellent problem‑solving skills.
At Koch companies, we are entrepreneurs. This means we openly challenge the status quo, find new ways to create value and get rewarded for our individual contributions. Any compensation range provided for a role is an estimate determined by available market data. The actual amount may be higher or lower than the range provided considering each candidate's knowledge, skills, abilities, and geographic location. If you have questions, please speak to your recruiter about the flexibility and detail of our compensation philosophy.
Who We Are
At Koch, employees are empowered to do what they do best to make life better. Learn how our business philosophy helps employees unleash their potential while creating value for themselves and the company.
Additionally, everyone has individual work and personal needs. We seek to enable the best work environment that helps you and the business work together to produce superior results.
