Company:
Qualcomm Semiconductor Limited
Job Area:
Engineering Group, Engineering Group > ASICS Engineering
General Summary:
As a leading technology innovator, Qualcomm pushes the boundaries of what's possible and drives communication and data processing transformation to help create a smarter, connected future for all. In this journey, Qualcomm is evolving into an AI-first intelligent-edge powerhouse, combining high-performance, low-power compute and seamless connectivity while pushing intelligence closer to users through ultra-efficient, on-device AI that ensures privacy, personalization, and real-time responsiveness. This is the Invention Age - and this is where you come in.
Job Overview And Responsibility
We are seeking a highly skilled engineer to develop 2.5D/ 3D chiplet and networking solution based technology-systems co-optimized for a unique era of heterogeneous compute as Moore's law slows down. The candidate is expected to be an expert in recent technology-architecture trends for heterogeneous low power high performance compute and AI compute. He/she should be able to apply that knowledge to influence Qualcomm's next generation SoC and platform architectures including partitions for logic and Cache, DRAM memories and involving 2.5D/3D chiplets and networking technologies to connect them. Knowledge of emerging optical networking technology is a plus.
Candidate will also drive innovation in the group and across Qualcomm's product BUs to effectively map emerging AI and other compute use cases to process and chip-integration solutions with detailed knowledge of process technology, 2.5D/ 3D chiplet architecture, networking technologies and trade-offs. Knowledge of different IPs e.g. CPU, GPU, NPU and how they act together to drive an E2E use case is a plus. Candidate will work with internal architecture and system teams to develop 2.5D/3D partitions and map to 3D stacking topologies. Candidate will perform system KPI analysis to drive 3D architecture and stacking strategies for new product introduction.
Minimum Qualifications:
- Experience with 2.5D and 3D STCO and pathfinding
- Excellent understanding of generic and AI use case KPI dependency on process and system architecture involving 2.5D/3D chiplets and networking technologies.
- Good knowledge of heterogeneous architecture, 2.5D/3D integration schemes.
- Basic programming skills e.g. ability to model e.g. in Python or other languages, system use case impact of 3D architectures, integration schemes.
- Master's or PhD in Electrical Engineering, Computer Science, or a related field
Additional Qualifications:
- Ability to work across teams and BUs
- Ability to work without supervision and as part of a team
- Most tasks do not have defined steps; simultaneous use of multiple mental abilities is generally required to determine the best approach
- Advanced data analysis and interpretation skills are required.
Minimum Qualifications
- Bachelor's degree in science, Engineering, or related field and 5+ years of relevant heterogeneous System and technology or related work experience. .
- OR
- Master's degree in Science, Engineering, or related field and 4+ years of heterogeneous System and technology or related work experience.
- PhD in Science, Engineering, or related field and 3+ years of heterogeneous System and technology or related work experience.
Minimum Qualifications:
- Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
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