Company
Qualcomm Semiconductor Limited
Job Area
Engineering Group, Engineering Group > ASICS Engineering
General Summary
We are seeking a highly motivated and experienced Engineer in Digital Yield Diagnostics to lead yield analysis and optimization for advanced-node semiconductor products. In this role, you will drive data-driven diagnostics, failure analysis, and yield improvement across the product lifecycle—from New Product Introduction (NPI) through high-volume manufacturing (HVM).You will work at the intersection of design, test, and manufacturing, leveraging large-scale data analytics, scan diagnostics, and statistical modeling to identify yield limiters and deliver actionable solutions. This role offers a unique opportunity to influence silicon quality, manufacturing efficiency, and product success at leading-edge technology nodes.
Key Responsibilities
- Lead yield diagnostics and analysis for advanced digital products across wafer sort, final test, and system-level validation.
- Drive root cause analysis of yield loss using scan diagnostics, electrical data, and statistical techniques.
- Partner with cross-functional teams (Design, DFT, Test Engineering, Foundry, and Operations) to resolve yield issues and implement corrective actions.
- Define and execute yield monitoring strategies, including dashboards, KPIs, and automated reporting systems.
- Drive continuous improvement in data infrastructure, automation, and diagnostic methodologies.
Qualifications
- M.S. or Ph.D. in Electrical Engineering or a related field, with 5+ years of relevant industry experience.
- Strong experience in yield analytics, diagnostics, and semiconductor data analysis.
- Proven track record of driving yield improvement in high-volume manufacturing environments.
- Solid understanding of Digital design architecture, DFT methodologies (scan, ATPG, etc.), and Test flows including ATE and SLT
Preferred Qualifications
- Experience with advanced node semiconductor process with hands-on experience driving yield ramp in HVM..
- Deep experience with scan diagnosis techniques and tools for volume yield analysis.
- Hands-on experience applying ML/AI techniques in yield analytics or diagnostics
Minimum Qualifications
- Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
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