power integrity , Perl, Python, Tcl, Sta, primetime, Cadence Innovus, Tempus, EM IR analysis, Voltus

production readiness , power analysis, Design Reviews, Silicon Bring-up, PnR Implementation, Verification, Physical Design, Placement, Floor Planning, ASIC Design, Low Power Verification, Rtl Design

Logic Design, Physical design architecture, P R Timing and Physical verification tools, floorplanning, Physical implementation flows, Physical design flows

Synthesis, physical verification closure, Formal, Timing Closure, block chip level implementation from Netlist to GDS, scripting skills – TCL

Routing, Sta, CTS, primetime, floorplanning, Pv, Tempus EDA suites, Cadence Innovus, Synopsys Fusion Compiler, LVS, Synthesis, EMIR, DRC

power optimization , FPGA Design, floorplanning, Place And Route, Timing Analysis, DRC/LVS Checks, Signal Integrity, Physical Verification, RTL Synthesis, Circuit Layout