Perl, Python, Timing Closure, Synthesis, Verilog RTL design, Low power design and low power flow, RTL design verification, Digital IP ASIC design, Post silicon validation, Design quality checks

Design for Testing (DFT), rtl development , System on a Chip (SoC) designs and integration, Verilog, Python, Perl, power analysis, LINT, processor design, cdc, arithmetic units, power closure, memory hierarchies, test plan and coverage analysis, FV, UPF checks, simulation debug, silicon bring-up, micro-architecture, bus architectures, Synthesis, ASIC SoC design verification, Timing, systemverilog, subsystem integration, accelerators, low-power design techniques

VXL, Analog Mixed-Signal Layout, Mentor Graphics Calibre, Custom Layout, EM, LVS, Dfm, VLE, IR verification, DRC, Antenna, Cadence Virtuoso

Python Scripting, IR EM Analysis, SI PI Analysis, Floorplanning and Power Planning, Physical Verification, STA and Timing Closure, Low Power Design UPF CPF, Physical Design and Signoff, Clock Architecture and CTS, Advanced Node Design Methodologies, AI-assisted Design Flows

Pcie, Systemc, Jenkins, Python, Perl, MATLAB, Design Verification, DV, Design Verification Lead, IP Verification, Subsystem Verification, systemverilog, Uvm, formal verification, Functional Verification, Constraint Random, Coverage Closure, Verification Plan, Specman E, Xcelium, Vmanager, Verilog-A, RNM, C Modelling, ISO 26262, Semiconductor, Pre-Silicon Verification

Clock Tree Synthesis (CTS), Routing, IR/EM analysis, floorplanning, Hierarchical and flat implementation flows, Physical Verification, Cadence Innovus, Timing analysis and optimization, Signoff methodologies, Timing Closure, Low-power implementation techniques, Signal Integrity, Noise issues

power integrity , Python Scripting, Static Timing Analysis, Chiplet Flows, Chiplet-level Physical Partitioning, Advanced-packaging, floorplanning, PD Methodology Flows, EM, IR-drop, LVS, Dfm, QoR Metrics, Place-and-Route, Physical Verification, Thermal-aware Placement, Physical Design, ERC, Timing Closure, DRC, Antenna

Shell, Perl, Python, Tcl, advanced Design languages, SOC IP Integration, Rtl Design