Python Scripting, silicon debug, FinSim, Circuit Simulation, MC analysis, nWave waveform viewer, Cadence, XA, Memory Compilers, waveform viewer tools, Silicon Failures Analysis, CMOS Circuit Design, Mentor schematic layout editor tools, XARA, Static and dynamic logic circuits, HSIM, Split rail Power gating Architecture, Hspice, layout design issues in sub nanometer regime, clocking scheme, Memory DFT

Perl, Python, Tcl, Statistical Analysis, SPICE simulations, PVT corners, transistor-level simulation, yield optimization, Cadence Virtuoso, SRAM Memory circuit design

rtl development , Vcs, Gdb, Shell, Perl, Verilog, Python, ASIC design flow, floor-planning, scripting knowledge, Simulation Tools, Timing Analysis, Logic Synthesis, debug tools, Eco, design and verification tools, micro-architecture, Debussy, bring-up lab debug