PCS, Mac, SVA, Ethernet architecture, Uvm, systemverilog, PHY interfaces

System Verilog, scripting for flow integration, AI ML-driven EDA tools, Uvm, C testcases, formal verification methodologies

Ethernet, Pcie, Synopsys, Uvm, advanced verification methodologies, systemverilog, Mentor, Cadence, PAM4, Register modeling, D2D, protocol VIP integration, Avery, PAM2

C, Systemc, Algorithm Development, Technical Leadership, MATLAB, Verilog, Python, Research Innovation, Cross-Functional Collaboration, System-Level Power Estimation, VHDL, Simulink, system modeling, Methodology Development

Functional coverage, Assertions SVA, Timing Constraints SDC, Physical Design PD, Uvm, Rtl Design, SystemVerilog SV, Verification

Tcl, Vcs, Python, Perl, Version Control, assertion-based verification, Questa, Uvm, verification methodologies, systemverilog, CI CD, RTL simulation, functional coverage

Tcl, Python, Shell, Soc Architecture, Rtl Design, UVM verification flows, Linux environments, Siemens Veloce, Synopsys ZeBu, systemverilog