routing, Sta, CTS, ECO execution, Pv, floorplanning, Dfm, constraints synthesis, Dft, Si, Timing Closure, block-level PnR, Netlist to GDS flow

Perl scripting, System Verilog, Python, PPA optimization, Cadence Innovus, advanced-node Block SoC designs, RTL-to-GDS implementation

Scripting, Perl, Tcl, Calibre, Innovus, Assura, Cv, ICC2, Cadence, EDA Tools, Verification Tools

C, Perl, Tcl, Clock Planning, Physical Verification, floorplanning, Placement and Routing, Timing Closure, Physical Design Implementation

static timing analysis, Synthesis, verification methodologies, design optimization techniques, low-power design methodologies, Power Planning, Place And Route, FC Innovus, Clock Tree Synthesis

routing, Shell scripting, Static Timing Analysis, Python, Perl, Ddr3, Tcl, Sta, IR drop, OCV, CTS, LVS, LPDDR PHY hardening, ECO implementation, antenna checks, MMMC, POCV, floorplanning, EM analysis, CRPR, Physical Verification, Signal Integrity, crosstalk, DRC, Timing Closure, Placement, ASIC Physical Design flow, DDR5, DDR4, AOCV

ICV or Calibre tools, block subsystem timing closure, physical design verification, full chip floor-planning and integration, IR EM analysis and resolution, block level and full-chip physical verification methodology, block physical design PDV and IR

routing, Verilog, Floor Planning, VHDL, Placement, Physical Verification, Clock Tree Synthesis, RTL to GDS flows

Static Timing Analysis, Frontend, Asic, Timing Closure, Physical Verification