Serdes Jobs

混合信號數位IC設計工程師(Serdes, 高速介面)

Permanent Job

Taiwan

0-2 years

CPHY fec FFE RTL digital circuit design Ethernet Serdes DP MPHY FIR IIR CDR CTLE EDA Tools HDMI Dsp Usb Pcie

6 days ago

Analog/Mixed-Signal Modeling Methodology Development Engineer

Permanent Job

Taiwan

0-2 years

Model Validation Environment revision management Verilog-AMS models Analog Mixed-Signal Design Digital and/or AMS Functional Verification SERDES Digital Design SystemVerilog Assertion systemverilog Finite State Machine Cadence Virtuoso DE Pll analog behavioral modeling EDA Tools Unix/Linux shell programming Verilog-A WiFi Makefile Perl Verilog Python

6 days ago

Product Marketing Manager (Retimer)

Permanent Job

Taiwan

5-10 years

retimer IC roadmap brochure SERDES redriver Monitor selection guide company profile Marketing Presentation Negotiation NB Collaboration product comparison table Report communication product promotion Workstation

6 days ago

ASIC 系統研發工程師

Permanent Job

Taiwan

0-2 years

??SerDes ???? SIPI ?? Embedded System C# C Python

6 days ago

SI/PI 信號完整性工程師/技術副理/技術經理

Permanent Job

Taiwan

2-4 years

HBM SI/PI ?? LPDDR4/3 Sigrity PowerSI Hspice EM ???? DDR4/3 Ansys HFSS/Siwave/Q3D Gbps SerDes SI/PI PDN IR drop ?? Spectre

6 days ago

Field Applications Manager

Permanent Job

Taiwan

3-10 years

altium IBIS-AMI make Keysight ADS Cadence Drivers PAM4 Mathworks QCD CXL NRZ SERDES Pcie Firmware Github BIOS Ethernet Python Gcc

a day ago

SENIOR MIXED SIGNAL IC DESIGNER

Permanent Job

Taiwan

7-10 years

analog designer synthesizer Clock and Data Recovery bicmos high-speed CMOS Pll SERDES lab equipment

8 days ago

Staff Engineer, Design Verification

Permanent Job

Taiwan

3-5 years

Serdes 112G/224G per lane Clauses CL72/92/136/162 High Speed PHYs Uvm DSP function hardware implementation knowledge systemverilog Ethernet PHY interoperability Systems C DPI/PLI formal verification C/C++ MATLAB Mac Perl Python

8 days ago

Technical Director, Design Verification

Permanent Job

Taiwan

10-12 years

high speed phys cross-discipline communication dv test plan serdes 112g/224g per lane Interpersonal Skills Problem-solving dpi/pli c/c++ Evaluation formal verification coverage driven constraints randomization testing vendor ethernet vips python/perl system simulation dsp function hardware implementation knowledge systems c interoperability Uvm testsuites clauses cl72/92/136/162 decision-making ethernet phy systemverilog Mac matlab Digital Logic Design

8 days ago

Senior Staff Engineer, Digital Verification

Permanent Job

Taiwan

6-8 years

Serdes 112G/224G per lane Clauses CL72/92/136/162 High Speed PHYs Uvm DSP function hardware implementation knowledge systemverilog Ethernet PHY interoperability formal verification C/C++ MATLAB Mac Perl Python

8 days ago

PI/SI design engineer/manager

Permanent Job

Taiwan

0-2 years

PI/SI simulation IBIS ENA-TDR instrument package PCB stackup optimization Ip Hspice Spectre simulation signal integrity simulation loss measurement Impedance S-parameter PCB Layout guide Optimization Spice models SERDES PCB modeling Usb Pcie DDR

8 days ago

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Serdes Jobs