Senior Verification Engineer

NVIDIA MMPLEX display teamdelivers cutting-edge IP solutions to multiple NVIDIA product lines, for example: GeForce, automotive etc.We are looking to grow our teams with the smartest people in the world, join us if you want to learn about world's leading IP technology and development process.
What you'll be doing:

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  Youwill participate in the research of verification methodology to improve automation and productivity to produce NVIDIA's new high-quality products.
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  Read IAS and design specs to understand the design requirement and build corresponding testplan. Review the testplan with arch/design engineers.
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  You responses to build block/IP testbench based on UVM methodology.
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  The responsibilities include building test run and regression flow. Triage failures in regression and help designer root cause the bug.
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  Work includes Build various metrics (passing rate, functional coverage, etc) and monitor its health.
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  Take SOC verification on fullchip test environment for IPs
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  Analyse functional/code coverage result and identify the coverage holes. Work with design engineer to improve the coverage score.
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  Deploy the advanced verification methodology and infrastructure of the SOC/IP

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  BS / MS in electrical / computer engineering and related.
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  3+ years (MS) or 5+ years (BS) working experience.
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  Familiar with advance verification methodology, tools and flow
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  Fully experienced verification flow, including testplan, test, coverage model, testbench, BFM modeling.
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  Deep understanding in Verilog and HVL (High-level Verification Language)

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  Strong programming skills in Perl and C/C++is plus
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  Having good arch/design experience is big plus.
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  At least good at one of the script programing language: Perl, Shell, Ruby, Python.
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  Fluent English (both written and spoken) and excellent communication skills.
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  Ability to work independently as well as in multi-disciplinary group environment.
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  Strong analytical skills.