1. Provide software and hardware solutions for ByteDance data center software and hardware projects, and consider the overall project plan and design based on the solution 2. Highly collaborate with the ByteDance hardware R&D team and business team to design and develop integrated software and hardware solutions . Ability to discover problems, raise issues, and solve problems from a solution perspective 3. Facing Bytedance business scenarios and combining industry solutions, propose targeted optimization and iteration plans to provide long-term and short-term goals and demand solutions for the project.
1. Bachelor degree or above, more than 5 years of relevant work experience 2. In-depth understanding of the entire technology stack from upper-layer software to underlying chips understanding and architectural capabilities. Including but not limited to having an in-depth understanding of io/network, CPU, business acceleration scenarios, AI and other fields 3. Requires experience in leading a team, being able to clearly plan and dismantle the team's goals and tasks, and having hands-on ability 4. Meet one or more of the following requirements: a. Familiar with Internet software and hardware business, understand business demands have participated in relevant solutions and implementation b. Familiar with NIC/RDMA and other core network protocol stacks and driver design implementation, familiar with computer networks, Understand the design, implementation, performance analysis and optimization of the collective communication library (ex: NCCL) and related algorithms (ex: Allreduce) c. Be familiar with the interconnection technology between GPU computing accelerator cards, including interconnection application scenarios, interconnection interfaces and interconnection networking be familiar with Typical interconnection solutions in the industry, familiar with communication libraries and source codes d. Have a certain understanding of memory consistency protocols and application scenarios such as CXL, and have experience in related heterogeneous memory architecture design e. Familiar with ARM/RISC-V SOC system architecture.