Computer Architecture, Verilog, System Verilog, Python, Logic Design, Tcl, Synthesis and Physical Design flows, Digital Design Techniques, device physics

UVM (Universal Verification Methodology), Tcl, Mercurial, Svn, DDR, Git, Perl, Pcie, Ethernet, Arm, Python, RISC-V, systemverilog, AMBA, Emulation, C/C++, System Verilog Assertions, Design Verification infrastructure

Vcs, Perl, Python, Tcl, Scan Insertion, Post-silicon validation, BScan, P1687, TetraMax, ATE patterns, JTAG protocols, Gate level simulation, Tessent tool sets, TestMax

Perl, Verilog, Python, Tcl, formal verification with Cadence LEC, Netlist CLP, Spyglass Lint CDC checks, UPF, clock domain crossing designs, Rtl Design, Synthesis, Logical Equivalence checks, low power design methodology

Perl, Python, Tcl, CDC Lint, low power design, digital circuit design principles, RDC, Timing Analysis Concepts, RTL design synthesis, UPF

static timing analysis, Python, Verilog RTL, Genus Design Compiler, scripting or programming languages, DFT methodologies, high-speed SerDes, ASIC synthesis, Asic Physical Design, physical verification DRC LVS, Cadence Virtuoso, 3DIC implementation methodologies, RTL Compiler, place-and-route Encounter Innovus ICC, Clock Tree Synthesis

Perl, Verilog, Vcs, Gdb, Python, Rtl Design, System-On-Chip design implementation, Debussy, Design Automation, dc shell