Python, Tcl, floorplanning, Physical design flows, Clock CTS, Logical Equivalence, Synthesis, Timing Analysis, EDA Tools, Budgeting, Physical Verification DRC LVS ERC, Place And Route

Power Delivery Networks (PDN), Ansys RedHawk-SC, Electromigration analysis, Cadence Voltus

Clock Tree Synthesis (CTS), Physical Design Planning, Placement, Floor Planning

hardware engineering , Perl Scripting, Sta, High Speed Cores, Circuit Level Comprehension, RTL to GDSII Implementation, Leakage Power, Signal Integrity, Multi-Vt Flow, Dfm, Power Supply Management, Deep Sub-Micron Design, Physical Design, Power Gating, High Frequency Design Convergence, PDN Methodology, PPA Targets, Timing Signoff

PYTHON, routing, PERL, Tcl, power analysis, physical design methodology, LVS, Physical Verification, noise analysis, Logic Synthesis, DRC, electro migration, Placement, Clock Tree Synthesis

Physical Design, Design for manufacturability, Timing closure methodologies, Placement and routing techniques, Clock Tree Synthesis, Design rule checks

Perl, Python, Tcl, Innovus, primetime, Calibre, StarRC, ICC2, Voltus

NDM Liberty .lib, Scripting, Timing Model Deliverables, AI-driven Automation, Physical Design, LibBuilder Flow, Library Management, AI-assisted Tools, MemView Generation, LEF, PVT Corner Coverage