Tcl Scripting, Perl, Python, primetime, ICC2, Cadence Innovus, Tempus, Synopsys Fusion Compiler, Synthesis, Ansys RedHawk, Timing Analysis, Physical Design Implementation

Routing, Physical Design, Synthesis, Timing Closure, LVS, EM, Ir, floorplanning, CTS, Sta, Power domains, Si, Placement, DRC, Hierarchical designs, RTL-to-GDSII flow, Physical Implementation

Flows, Physical Design, verbal and presentation skills, Design Methodologies, debugging skills, sign-off tools