Logic Equivalence Checking (LEC), Static Timing Analysis (STA), Python, Tcl, RTL Synthesis, Low Power UPF IEEE 1801, primetime, Fishtail

OASIS, Verilog, Python, Shell, Perl, Tcl, PERC, LVS, Physical Design, Dfm, CDL, SVRF-based automation, XOR methodologies, antenna density, ASIC physical verification, Spice, Cadence Pegasus, DEF, LEF, Siemens Calibre nmDRC, metal-fill, ERC, DRC, Synopsys ICV, GDSII

static timing analysis, RISC CPU IP, CPU microarchitecture, IP integration, Floor Planning, silicon bring-up, Timing Analysis, Emulation, Physical Design, chip validation, Rtl Design, CDC analysis, ARM CPUs, SoC design methodology, characterisation, Synthesis, linting, Timing Closure, Verification, equivalence checking, BUS Protocols

Networking, Sql, Java, AWS, Nosql, Python, Kubernetes, Gcp, Apache Kafka, Cloud Security, Cloud Computing, GCP Pub Sub, Ai

Formal verification (LEC), Static Timing Analysis (STA), Perl, Python, Tcl, Logic Synthesis, Physical-Aware Synthesis, PPA optimization, systemverilog, UPF management

C, C++, Dac, Scripting, Python, LabVIEW, ADC, mixed-signal ICs, sensing solutions, lab instrumentation, AFE data-acquisition, analog signal-chains, embedded MCU, RISC-V, Pcb Design, reference designs, PGAs, evaluation boards, sensor excitation, low-noise amps, precision power supplies, ARM subsystems

arm architecture , Uart, Pcie, Verilog, I2c, Flash, digital ASIC design, low power methodology, system debug infrastructure, RTL level checks, systemverilog, AMBA bus protocols, SSP, system memory hierarchy, ARM based ecosystem components, multi-core SOC designs, DRAM, ARM v8 and v9 specifications, DC DC-T based synthesis

Tcl, Verilog, Python, Perl, MBIST, Siemens Mentor Tessent, systemverilog, ATPG, Pre-Silicon test planning, DFT methodologies, DFT Compiler, low power concepts, RTL design for DFT, Scan, IJTAG, Synopsys TetraMAX, DFT Integration Verification, Memory Repair