Formal verification (LEC), Static Timing Analysis (STA), Perl, Python, Tcl, Logic Synthesis, Physical-Aware Synthesis, PPA optimization, systemverilog, UPF management

rc extraction , Python Scripting, hierarchical design methodologies, IR EM Voltus, DRC LVS Calibre flows, power intent, Cadence Innovus PNR tool, STA PrimeTime, clock mesh tree design

synopsys primetime , Perl, Python, Tcl, Unified Power Format UPF, Tweaker, Constraints Validation Synopsys TCM GCA Ausdia TimeVision SpyGlass Constraints, Cadence CCD, Sign-off STA Synopsys PrimeTime PT PT-PX, PrimeClosure, Cadence Tempus, Synopsys Formality, Timing Closure ECO Cadence Tempus

static timing analysis, Rtl Design, Synthesis, RISC CPU IP, Emulation, silicon bring-up, Microarchitecture, Verification, equivalence checking, Physical Design, CDC linting

Unix Shell, DDR, Pcie, Perl, Ethernet, Python, Tcl, SOC inter-connect buses, Palladium, coding in scripting languages, Processor Architecture, SOC components, IO protocols, Zebu, HBM, Veloce, CXL, memory technologies, emulation platforms

static timing analysis, LINT, Logic Synthesis, cdc, formal verification, Dft, Cadence-based ASIC design environments, low-power design methodologies, micro-architecture development, SystemVerilog RTL design

Integration, Programming Languages, architecture and design tools, scripting tools, ASIC Design, Verification, design verification methods, RTL to GDS Flow, virtuoso, Validation