Doors, Continuous Integration, Change Management, Jira, MATLAB, Jama, Video Processing, automation systems, SV, FPGA EDA tools, Lifecycle Program Management, Subversion, high-speed serial protocols, Uvm, Microsoft Project, earned value management, DO-254 compliance, VHDL, ASIC Design, Model-Based Design

Formal Property Verification (FPV), Perl, System Verilog, Python, ASIC SoC Design Verification, Uvm

shielding , custom layout design, signal flow optimization, isolation, device matching, LVS, Power Planning, layout architecture, IR optimization, clock routing, parasitic minimization, power routing, biasing, EDA Tools, ERC, DRC, Cadence Virtuoso, EM IR latch-up prevention, parasitic management, ESD protection

multi-domain clock synchronization, spyglass, high-speed serial interfaces, Verplex LEC, ASIC debugging, high-performance memory subsystems, Synopsys Design Compiler, Verilog RTL coding

static timing analysis, Verilog, VHDL, Xcelium, RTL Coding, design-for-test

DVCS e.g. Git, Sql, C, Xpath, Gcc, HTML, Xslt, Dom, Linux, Xml, Python, Javascript, LLVM, Uvm, SGE or other DRMS, systemverilog, Assembly languages, SVA