Logic Equivalence Checking (LEC), Static Timing Analysis (STA), Python, Tcl, RTL Synthesis, Low Power UPF IEEE 1801, primetime, Fishtail

Verilog, formal verification, VHDL, Chisel, JasperGold, VC Formal, Object-oriented Programming, Formal Abstraction Techniques, systemverilog

Nosql, Databases, Docker, OLAP, Distributed Systems, Rest Apis, Python, Kubernetes, AWS, Oltp, AI-native development

Unix, Shell, Linux, Verilog, Python, Tcl, Synthesis, cdc, Simulation, RTL, make, systemverilog, RDC, LINT, Low Power

data engineering , react.js , Data Modelling, Azure Data Bricks, Microservices, Data Quality, Typescript, Distributed Systems, Rest Apis, Python, LLMs, RAG systems, vector databases, agent frameworks, AI integration, large-scale data processing, ETL pipelines

static timing analysis, RISC CPU IP, CPU microarchitecture, IP integration, Floor Planning, silicon bring-up, Timing Analysis, Emulation, Physical Design, chip validation, Rtl Design, CDC analysis, ARM CPUs, SoC design methodology, characterisation, Synthesis, linting, Timing Closure, Verification, equivalence checking, BUS Protocols