Python, Tcl, floorplanning, Physical design flows, Clock CTS, Logical Equivalence, Synthesis, Timing Analysis, EDA Tools, Budgeting, Physical Verification DRC LVS ERC, Place And Route

Power Delivery Networks (PDN), Ansys RedHawk-SC, Electromigration analysis, Cadence Voltus

Clock Tree Synthesis (CTS), Physical Design Planning, Placement, Floor Planning

Multi-mode Multi-corner (MMMC), Clock Tree Synthesis (CTS), Static Timing Analysis (STA), Shell, Python, Routing, Perl, Tcl, OCV, primetime, Power Grid Analysis, Fusion Compiler, ICC2, Tempus, Voltus, Innovus, SDC, Static Dynamic IR Drop, Placement, Setup Hold, POCV, RedHawk-SC, floorplanning, Physical Design, Timing Closure, EDA Tools, AOCV

hardware engineering , Perl Scripting, Sta, High Speed Cores, Circuit Level Comprehension, RTL to GDSII Implementation, Leakage Power, Signal Integrity, Multi-Vt Flow, Dfm, Power Supply Management, Deep Sub-Micron Design, Physical Design, Power Gating, High Frequency Design Convergence, PDN Methodology, PPA Targets, Timing Signoff

Physical Design, Design for manufacturability, Timing closure methodologies, Placement and routing techniques, Clock Tree Synthesis, Design rule checks

Perl, Python, Tcl, Innovus, primetime, Calibre, StarRC, ICC2, Voltus

Power Delivery Networks (PDN), Ansys RedHawk-SC, Electromigration analysis, Cadence Voltus

Routing, Sta, CTS, floorplanning, EM, Ir, LVS, Physical Implementation, RTL-to-GDSII flow, Synthesis, Physical Design, Placement, Si, DRC