boundary scan , Jtag, Scripting, Tcl, multi-clock domain designs, DFT signoff, scan architecture, MBIST, DFT architecture, Timing Constraints, ATPG, clocking architectures, silicon bring-up, LBIST, manufacturing test flows, compression methodologies

Vcs, Tcl Scripting, Python, Sta, Synthesis, cdc, SoC integration, Xcelium, QuestaSim, RTL lint, clock reset architecture, systemverilog, quartus, RDC, Vivado, Timing Closure, memory mapping, AMBA AXI AHB APB protocols, ip development

conformal lec , Clp, Tcl, Python, Perl, Cadence Genus, Synthesis, UPF, LEC, MCMM methodologies, Fusion Compiler, RTL-to-GDS, Low Power Verification, CPF, Formality, Synopsys Design Compiler

Microprocessors, SoC development, clock rate compensation, high-speed serial IO protocols, FIFO gearbox design, coverage metrics, Verification, controller power gating, managing IP dependencies, full-chip design, Synthesis, memory controller designs, planning front-end design tasks, low power modes, reviewing high-level test plans, design convergence cycle, Timing Closure, architecture, data width bypass, micro-architecture

static timing analysis, Perl, Tcl, Synthesis, Makefile scripting, physical design CAD flow, Mentor Calibre, Power Distribution, hierarchical P&R, Cadence Innovus, Cadence Genus, Floor Planning, physical design verification