C, Pcie, Ethernet, SV, CXL, UCIe, Uvm, systemverilog, SVA

C, Verilog, Verdi, Xcellium, JasperGold, Uvm, systemverilog

Object Oriented Programming, Shell, Perl, Python, Make file, Power aware verification, Gate-Level Simulation, System Verilog UVM, Mentor, Cadence, UPF, C based and assembly level testcases, Assertions, System Verilog Testbench Architecture, HDL such as Verilog SystemVerilog, Processor Architecture, Processor Verification, HVL such as SystemVerilog testbench OVM UVM, TCI, Synopsys, formal verification, Digital Design

synopsys primetime , Tcl Scripting, Timing exceptions, SDC constraints, Design Compiler, OCV, Constraint debugging, Skew, Latency, PVT corner analysis, Setup hold timing, Clock definitions, Timing derates, Signal integrity effects, Synthesis optimization, RTL-to-gate synthesis, POCV, PPA trade-offs, Root-cause resolution, Clock uncertainty, AOCV, Timing-driven mapping, MMMC analysis

C, C++, Verilog, Tcl, Python, Xml, Perl, systemverilog, formal verification, Assertions, UVM methodology, Synopsys, Verification simulation, Silicon process technologies, Coverage-driven verification, Cadence, VHDL, Formal debug, Constrained-random testing, Regression management, SoC verification environments

Test Automation, Git, Shell Scripting, Python, Validation, TCP IP Networking, WLAN 802.11, quality engineering, CI CD

Tcl, Python, Perl, Innovus, Physical Formal Verification, Cross-Functional Collaboration, LEC, primetime, EDA Tools, Fusion Compiler, Calibre, Red Hawk, Tempus, Timing Closure STA, RTL-to-GDSII Execution, Programming Scripting, VCLP, PPA Optimization