Perl, Python, Tcl, Timing Closure STA, RTL-to-GDSII Execution, Red Hawk, Programming Scripting, Fusion Compiler, LEC, Tempus, Cross-Functional Collaboration, Physical Formal Verification, Innovus, Calibre, primetime, PPA Optimization, EDA Tools, VCLP

Python, FineSim, Synopsys VCS, Skill, Xcelium, Verilog-AMS, SystemVerilog-RNM, Cadence Virtuoso, Spectre

Memory Management, virtualization, System Verilog, Python, Perl, HW-SW debug, Uvm, power management fundamentals, Functional Coverage, DV test bench, Virtual Memory concepts, Scoreboards, Post-Silicon bring-up, coherency protocols, IP Sub System design verification, Assertion, Checkers, Trackers

Apis, Node.js, Microservices, Angular, Testing Frameworks, Typescript, Javascript, System Design, CI CD, service-oriented architecture, Object-Oriented Design, observability

Java, Scala, Distributed Systems, Python, Go, Backend Systems Infrastructure

Usb, Networking, Nvme, Storage, Graphics and Display, Python automation frameworks, Root Cause Analysis, Platform Validation, Post Silicon Validation, Platform Debug, System Debug, Platform security, RAS technologies, Windows platform debugging, Validation infrastructure development, PCIe Gen4 Gen5, Silicon-to-system interactions, DDR4 DDR5 Memory

Schematic design, MATLAB, Python, Synopsys Custom Compiler, BERTs, Spectre, Hspice, Cadence Virtuoso, Layout interaction, behavioral modeling, Lab measurements, BER estimation, High-speed oscilloscopes, Post-layout verification, Design sign-off, Jitter budgeting, Parasitic Extraction, Silicon bring-up