Clock Tree Synthesis (CTS), Static Timing Analysis (STA), Routing, Perl, Shell scripting, Python, Tcl, floorplanning, Cadence Innovus, Power Planning, Calibre, Placement, Timing Closure, Physical Design implementation, Synopsys Fusion Compiler ICC2

Perl, Python, Tcl, Innovus, Calibre, Assura, ICC2, Cadence, Synopsys, ICV

Physical Design Implementation, Synthesis, Timing convergence, Synopsys ICC2, Cadence Innovus, Standard place-and-route flows, AI technologies, Place And Route, Clock Tree Synthesis, RTL-to-GDSII flow, Layout closure