Systemc, Test Planning, C, Shell, Tcl, Verilog, Python, systemverilog, NoC bus and interconnect verification, assertions, transaction-level modeling, UVM-based testbench development, constrained-random verification, formal verification, power-aware verification

Verilog, SVA, formal verification, Assertions, Uvm, debugging complex RTL, systemverilog, Functional verification methodologies, testbench issues, Coverage

System Verilog, UVM methodology