C, Uart, Bash, Spi, Pcie, Perl, Verilog, I2c, Python, Tcl, DFx Verification, RTL simulation, Palladium emulation, i2s, Gate-Level Simulations, Uvm, systemverilog, FPGA prototyping, Axi, APB, LPDDR, AHB

Apis, PowerShell, configuration management, Siem, Rest Apis, automation, Python, security telemetry platforms, operational dashboards, CI CD processes, infrastructure-as-code, Google SecOps, cloud-native services

static timing analysis, Perl, Verilog, Python, Tcl, Rtl Design, Synthesis, Dft, ATPG, systemverilog

code coverage , C, Shell, Perl, Verilog, Debugging, Python, System Verilog, Tcl, UVM methodology, Metric Driven Verification, formal verification methodologies, assertions, constrained random methodologies, functional coverage

Perl, Python, Sequencers, Agents, Checkers, Uvm, Functional coverage, systemverilog, Assertions, Coverage models, Verilog-AMS, Verification methodology, Scoreboards, Monitors, Constrained random techniques, Verilog-A