database qa , simulations , manufacturing processes , Cadence, SRAM architectures, Synopsys, Design Architecture, Advanced technology nodes, Low-power memory circuit design, Model generation, Memory design flows, Sram, Layout supervision, Compiler automation, CAD Tools, Prototype testing equipment, Circuit implementation, Memory technologies, Circuit schematics, characterization, Yield optimization, Signal Integrity, Timing Analysis

Perl, Verilog, System Verilog, Python, Tcl, Systemc, AI-enabled automation workflows, make, AI Agent

Shell, C++, Perl, Verilog, System Verilog, Python, Systemc, Tcl, AI-enabled automation workflows, make, AI Agent

Shell, Perl, Verilog, System Verilog, Python, Tcl, Systemc, AI-enabled automation workflows, make, AI Agent

C, Perl, Verilog, Python, Uvm, systemverilog