Scripting, EMIR Signoff flow, Data Analysis, In-rush current profiles, EDA Tools, Dynamic vectored and vectorless Static IR, Power Distribution Network Design, On-die power gating, Problem Solving

Sta, PG creation and push-down methodologies, Physical Verification, SoC RTL to GDSII implementation, Scripting flow deployment, RDL knowledge, SoC Full-chip floorplanning, Die file generation, Feed-through planning, Hierarchical design implementation, PnR implementation

Logic Design, Physical design architecture, P R Timing and Physical verification tools, floorplanning, Physical implementation flows, Physical design flows

flows and methodologies, Asic Physical Design, collaboration and teamwork, EDA vendor relationships

power integrity , Perl, Python, Tcl, Sta, primetime, Cadence Innovus, Tempus, EM IR analysis, Voltus

Scripting, EMIR Signoff flow, In-rush current profiles, Data Analysis, EDA Tools, Dynamic vectored and vectorless Static IR, Power Distribution Network Design, On-die power gating, Problem Solving

Automation Frameworks, Perl, Python, Tcl, AI-native automated methodologies, Methodology, Physical Design, Sub-3nm device physics

caliber , Clp, Tcl, Python, Synopsys Fusion Compiler, UPF, Signoff, multi-voltage, PD tools and flows, Cadence Innovus, low power flows, Sta, ICC2, primetime, physical design implementation, ICV, Tempus, Synthesis, multi-Vt, PNR, Ansys RedHawk, RTL-to-GDSII flows