C, Clearcase, Cryptography, Aes, Encryption, Clearquest, Perl, Verilog, Python, System Verilog, LINT, cdc, RTL design using Verilog, hash functions, GMAC, signatures, LEC, SHA, private key, ASIC development tools, random number generator

rtl development , static timing analysis, Verilog, Digital Signal Processing, LINT, Synthesis, Debug, LEC, Simulation, Matlab modeling, FPGA prototyping

Verilog, Python, Synopsys, Cadence Tools, performance modeling tools, arithmetic units, accelerators, memory hierarchies, low-power design techniques, bus architectures

catapult , Vcs, Ecos, Verilog, System Verilog, spyglass, LINT, Timing Analysis, Synopsys DC, cdc, Rtl Design, Verdi, VHDL, Stratus, Xcellium, SDC, Dft, Magillem, low power design methodologies

Verilog, Logic Design, Physical Design, cdc, Timing Constraints, RTL constraints, Vlsi, LINT, timing exceptions, System-Verilog

Verilog, Timing analysis closure, Power analysis optimization, RTL Coding, CPU Core RTL Design, systemverilog

Spi, Embedded Controllers, Verilog, I2c, Uart, Can, cdc, testability requirements, Simulation, Dft, Synthesis, linting, Motor Control Systems, RTL Coding, GPIO Timers, debug activities, PWM Modules, Scan Insertion, DMA Interrupt Controllers, Ethernet Interfaces, systemverilog, Quality Checks, Functional Verification, Physical Design, Industrial Communication Interfaces