Usb, Pcie, Perl, Verilog, Python, Makefiles, RTL Build flows, AMBA protocols, Debug architecture, Axi, SoC Clocks, SDCC, APB, RST, SOC design, AHB, System-Verilog

Verilog, System Verilog, Linear Control Theory, power management, High Bandwidth Linear Amplifiers, Cadence ADE, Transistor Reliability, UVI Techniques, Mixed signal circuits, Electro-Migration, behavioral modeling, Very Low Power References, Analog Front Ends, MathWorks MATLAB, High Accuracy Data Converters, Power Electronics, VerilogAMS

code coverage , C, Shell, Perl, Verilog, Debugging, Python, System Verilog, Tcl, UVM methodology, Metric Driven Verification, formal verification methodologies, assertions, constrained random methodologies, functional coverage

Verilog, Python, SDC, DEF, AI LLM-based tooling, UPF, LEF

conformal lec , Python Scripting, Verilog, primetime, Fusion Compiler, Genus, Tempus

Perl, Python, Sequencers, Agents, Checkers, Uvm, Functional coverage, systemverilog, Assertions, Coverage models, Verilog-AMS, Verification methodology, Scoreboards, Monitors, Constrained random techniques, Verilog-A

static timing analysis, Perl, Python, LINT, EDA tools for synthesis, cdc, digital design principles, verification methodologies, RTL design using Verilog, clocking resets, Simulation, Timing Analysis, RTL quality tools such as Spyglass, RDC, VHDL, low-power design techniques

C, Uart, Bash, Spi, DDR, Perl, Pcie, Verilog, I2c, Python, System Verilog, Tcl, i2s, DFX Verification, Uvm, Axi, APB, AHB

Can, Device Drivers, Uart, I2c, Control Algorithms, Spi, Embedded Control Firmware, Microcontrollers, Control Loop Simulation, Power Electronics