static timing analysis, Perl, Verilog, Python, Tcl, Rtl Design, Synthesis, Dft, ATPG, systemverilog

Verilog, System Verilog, Linear Control Theory, power management, High Bandwidth Linear Amplifiers, Cadence ADE, Transistor Reliability, UVI Techniques, behavioral modeling, Electro-Migration, Mixed signal circuits, Very Low Power References, MathWorks MATLAB, Analog Front Ends, High Accuracy Data Converters, Power Electronics, VerilogAMS

C, Verilog, System Verilog, Verdi, Xcellium, JasperGold

OASIS, Python, Shell, Perl, Tcl, PERC, LVS, CDL, Dfm, SVRF-based automation, Verilog netlists, XOR methodologies, layout connectivity, antenna density, ASIC physical verification, Spice, Cadence Pegasus, DEF, LEF, Siemens Calibre nmDRC, metal-fill, ERC, DRC, Synopsys ICV, GDSII

Power Bi, Agile Methodology, GitHub Copilot, AI ML solutions, Generative AI concepts, Model Context Protocol, workflow automation, project management methodologies, program management

Matlab Simulink, RTL Verilog, mixed-signal verification, digital PWM modulators, digital design tools, systemverilog