virtualization, Memory Management, Perl, Python, System Verilog, IP Sub System design verification, Functional Coverage, Trackers, Assertion, Checkers, HW-SW debug, Uvm, power management fundamentals, coherency protocols, DV test bench, Scoreboards, Post-Silicon bring-up, Virtual Memory concepts

static timing analysis, Perl, Python, LINT, EDA tools for synthesis, cdc, digital design principles, verification methodologies, RTL design using Verilog, clocking resets, Simulation, Timing Analysis, RTL quality tools such as Spyglass, RDC, VHDL, low-power design techniques

Java, Kafka, Python, API design, Incident Management, Gcp, Distributed Systems, Kubernetes, Testing, Go, Alerting systems, Flink, Microservices architecture, developer tools, Streaming Data, SDKs, Monitoring

react.js , Golang, Python, Sql, GenAI, Google BigQuery

cadence spectre , Python, Synopsys VCS, Skill, Verilog-AMS, SystemVerilog-RNM, Cadence Virtuoso, AMS verification, SerDes verification, Optical simulation tools, Ansys Lumerical, Synopsys OptoCompiler, Uvm, High-speed design, Mixed signal modelling and verification