Perl, Shell scripting, Python, Tcl, Circuit Simulation, IC design, Chip assembly and physical verification, Flow automation regression testing, Place Route, Physical design Netlist to GDSII Flow, Layout, EDA Tools, ASIC Design, Power Clock Distribution, Timing power noise DFM optimization and analysis, Tool evaluation and improvement, Timing Analysis

Perl, Shell scripting, Python, Tcl, Layout, EDA Tools, IC design, Circuit Simulation, Timing Analysis, digital circuit design, Place Route

Python, Tcl, Function eco creation, Timing budget, Constraints creation and validation, RTL netlist quality check, Chip partitioning, Timing Closure, Synthesis, formal verification, Chip Integration, Floorplan, Netlist generation, Flow automation development