synopsys primetime , Perl, Shell scripting, Python, Tcl, place-and-route, Synthesis, timing exceptions, ECO implementation, MMMC timing analysis, jitter, clock skew

redhawk , Tcl Scripting, Python, timing reports, primetime, Fusion Compiler, floorplanning, CTS routing, Tempus, LEC, Cadence Innovus, Physical Verification, setup hold debugging, Voltus, tile block PnR, Calibre, Asic Physical Design, Optimisation, StarRC, Parasitic Extraction, Placement, Synopsys ICC2

Static Timing Analysis, Python, Tcl, SDC constraint authoring and management, primetime, Fusion Compiler, Physical-Aware Synthesis

redhawk , Shell, PERL, Verilog, Tcl, place and route methodologies, low power physical design flows and methodologies, Fusion Compiler, physical implementation and analysis tools, timing and signal integrity analysis, Innovus, Calibre, VHDL, power integrity and reliability analysis, power grid planning and implementation, Starrcxt, timing optimization and timing closure, placement and optimization, metal-only ECO implementation, floorplan exploration and optimization, Clock Tree Synthesis

Sta, power analysis, PDN analysis, CTS, Physical Verification, Dfm, Physical Design, Timing Closure, ASIC Implementation, Dft, Synthesis, Timing Closure, Floor Planning, logical and physical optimization, Structured clock tree, Place And Route

redhawk , Verilog, Fusion Compiler, Metal-only ECO Implementation, Timing Optimization, Signal Integrity Analysis, FLASH Process Technologies, Floorplan Exploration, Innovus, Calibre, low power design, GDSII Flow, VHDL, Physical Design, Starrcxt, Reliability Analysis, Clock Tree Synthesis

power integrity , Routing, CTS, primetime, Fusion Compiler, floorplanning, ICC2, PDN Placement, Physical Verification, Calibre, Innovus, SoC ASIC Physical Design, Timing Closure, signoff methodologies