static timing analysis, Perl, Verilog, Python, Tcl, Rtl Design, Synthesis, Dft, ATPG, systemverilog

UNIX, Verilog, Debugging, design quality checks, SoC connectivity concepts, Simulation, RTL integration, Digital Design, Windows environments, systemverilog, RTL Coding, Ms Office Tools, ASIC SoC design methodologies

receivers , Pcie, analog circuits simulation, mixed-signal analog integrated circuit design, PLLs, jitter compliance simulations, SERDES, clock drivers, ADCs, differential buffers, FLLs

Firmware Development, FPGA Design, Verilog, Static Timing, ASIC design flow, Synthesis, datapath timing analysis, digital design principles, high-speed data transmission, systemverilog, CMOS digital circuits, Rtl Design, Dft, front-end tools, mixed signal concepts, Verification, clock design

Shell, Tcl, Verilog, Python, Perl, Modelsim, Uvm, LINT, Questa Formal, systemverilog, JasperGold Formal, Cadence VCS, VHDL, Makefiles, QuestaSim, Cadence Xcelium

Power EM IR-drop analysis, Synthesis, Full-chip hierarchical floorplanning, RTL-to-GDSII implementation, Linting, UPF-driven low-power design methodologies, Parasitic Extraction, Timing SI power closure

control logic , Verilog, Rtl Design, Synthesis, systemverilog, Error handling, cdc, Sta, Ethernet standards, Digital micro-architecture, PCS functionality, Link monitoring, state machines, Packet processing, RDC, Safety mechanisms

Verilog, System Verilog, Synthesis, VHDL, digital timing analysis, RTL Coding, lint CDC RDC constraint development, RTL micro architectures development, Digital Design

static timing analysis, Synthesis, multi-power-domain design techniques, Simulation, Uvm, FPGA design methodologies, formal verification tools such as Siemens Questa Formal and Synopsys Spyglass