Usb, Mac, Pcie, Perl, Ethernet, Shell scripting, System Verilog, Python, Tcl, AHB-Lite, Uvm, AMBA, Axi, APB

Fpga, Perl, Python, Emulation, RTL, Uvm, systemverilog

Pcie, System Verilog, Python, Systemc, Hybrid test benches, MDV, DV signoffs, SV, Uvm, UCIe, Axi, CDV

Verilog, Scripting Languages, Verification Tools, VHDL, Uvm, formal verification, Simulators

Shell, Perl, Python, Tcl, Debugging RTL verification issues, Assertions SVA, SoC IP architecture and verification methodologies, UVM methodology, systemverilog, Functional Verification, Coverage-driven verification

cache coherency , Uvm, DMA engines, ARM-based SoCs, memory systems, systemverilog, Transaction-level verification, CHI, Ace, AXI NoC architectures

simvision , python, Cadence simulation tools, Uvm, Xcelium, netlist simulation

Perl, Vcs, Python, Tcl, Uvm, Verdi, Questa, systemverilog

Python), Universal Verification Methodology (UVM), test environments , scoreboard , Scripting languages (Perl, C, C++, Soc Architecture, Shell, Verilog, Test Cases, Sequencers, Mixed signal designs, Debugging RTL and Gate simulations, Industry-standard simulators, Agents, Revision control systems, Verification testbenches, Testbenches, Regression systems, Verification methodology, Directed and constrained random verification methodology, Monitors