FEA tools, Debugging, Control loop theory, PCB CAD tools, power management, Circuit Design, Board level analog and digital circuit design, Data analysis using Excel or JMP, PCB schematic design, Troubleshooting

Arm, Python, RTL simulation, Debug, functional coverage closure, RISC-V, regression automation, x86 architecture, Uvm, SVA, systemverilog

Tcl Scripting, Computer Architecture, Scala, formal verification methodologies, model checking, digital design principles, ASIC Design, Chisel, assertion-based verification, equivalence checking

C, Debugging, Python, CPU architecture, Validation, Assembly Programming

Rtos, Usb, Gdb, Bics, Uart, Spi, Svn, JIRA, Git, Jtag, Bitbucket, I2c, C Programming, Python, Data Sheets, NAND flash memory, TIMER, RISC-V microcontroller architecture, reading schematics, code collaborator, NAND Programming, Threadx, DMA

hardware engineering , C, Jtag, Verilog, Scripting Languages, System Verilog, IEEE1500, HDLs, memory dump, MBIST, scan dump, formal verification methodologies, CPU micro-architectures, CPU architectures, power management features, testbench components

OASIS, Python, Shell, Perl, Tcl, PERC, LVS, CDL, Dfm, SVRF-based automation, Verilog netlists, XOR methodologies, layout connectivity, antenna density, ASIC physical verification, Spice, Cadence Pegasus, DEF, LEF, Siemens Calibre nmDRC, metal-fill, ERC, DRC, Synopsys ICV, GDSII

.Net Core, .NET Standard, C#, Kafka, Devops, Software Architecture, Authentication, API versioning, Agile, ASP.NET, High-performance scalable systems, Backwards compatibility, Rate limiting, RESTful API design, CI/CD, Micro-services, Cloud design patterns