power integrity , Routing, CTS, primetime, Fusion Compiler, floorplanning, ICC2, PDN Placement, Physical Verification, Calibre, Innovus, SoC ASIC Physical Design, Timing Closure, signoff methodologies

Verilog, Python, Tcl, Physical Verification, Sign-off Optimizations, High Performance Synthesis, Constraints Synthesis, Physical Design, Electrical Checks, systemverilog

static timing analysis, industry-standard EDA tools for physical design and verification, Synthesis, RTL-to-GDS workflows, multi-power domain analysis, Place And Route, low-power design techniques, Clock Tree Synthesis

Perl scripting, Tcl Scripting, Python, Sta, setup hold analysis, floorplanning, CTS routing, Cadence Innovus, physical optimization, LVS, MMMC-based implementation, full-chip Physical Design, ECO implementation, physical and timing ECOs, Dft, RTL synthesis, Timing Closure, DRC, Placement

power integrity , Routing, CTS, floorplanning, Low-Power Design, Synthesis, Physical Verification, Timing Closure, Placement, Sign-off, Multi-Voltage Domains, Physical Design implementation

Routing, RTL synthesis, Placement, Floor Planning

routing, Tcl Scripting, Shell scripting, Python, Perl, MCMM setup hold OCV AOCV POCV, CTS, primetime, Fusion Compiler, Crosstalk, Tempus, Cadence Innovus, LVS, Power Planning, post-route optimization, IR Drop, STA timing closure, RTL-to-GDSII Physical Design flow, floorplanning, EM Signal Integrity, signoff, Physical Verification, Eco, DRC, Placement, Synopsys ICC2