Tcl, System Verilog, Python, Perl, Vcs, Questa, Uvm, Modelsim

code coverage , SoC Verification, MCU Verification, Uvm, Functional Coverage, Assertion Coverage

Coverage models, CPU Core Verification, Constrained-random tests, Scoreboards, Checkers, Architecture Validation, Uvm, systemverilog, Testbenches

Cadence - Virtuoso, Perl, Python, Tcl, Mentor tools, SV, Verilog Hdl, Cadence, Uvm, Spice Simulator, Verilog-AMS, AMS simulation environment, Verilog-D, Synopsys, Verilog-A

Perl, Pcie, Python, Tcl, SV, ONFI, MBIST, AI tools and Methodologies, Uvm, NAND, DFT architecture, LPDDR, Test controller architecture

Usb, C, C++, Debugging, Test Plan, Object Oriented Programming, Writing Test Cases, Oop, DDR, Ethernet, Pcie, Perl, Tcl, Function coverage, Coverage driven verification, Uvm, IP Subsystem SOC ASIC Verification, Axi, Code coverage analysis, CXL, Test bench development, Simulation, System-Verilog

Verilog, System Verilog, Synopsys VCS, Cadence IES, formal property checking tools, Uvm