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Job Summary

We are seeking a highly experienced Principal Verification Engineer to lead and drive functional verification for complex ASIC/SoC designs. This role requires deep technical expertise, strong architecture-level thinking, strong understanding of Ethernet specifications, and the ability to mentor teams while ensuring delivery of high-quality silicon. The ideal candidate will own verification strategy end-to-end and work closely with design, architecture, and post-silicon teams. The candidate will play a key role in ensuring standards compliance, performance, interoperability and robustness of ethernet products.

Key Responsibilities

Technical Leadership

Define and own verification strategy and methodology (UVM/SystemVerilog) at IP, subsystem, and SoC levels
Thoroughly understand and interpret Ethernet and related protocol specifications (IEEE standards, architecture specs, and micro-architecture documents) and translate them into comprehensive verification plans, assertions, and test scenarios
Architect scalable verification environments, reusable VIPs, and checkers
Drive coverage-driven verification, including functional, code, and assertion coverage
Lead verification planning, testbench architecture, and test plan sign-off
Identify, Review and guide complex test scenarios and corner cases

Execution & Quality

Ensure first-pass silicon success through rigorous functional and protocol compliance verification
Drive bug triage, root-cause analysis, and closure across IP, Subsystem and SoC levels
Define and track verification metrics, quality KPIs, and sign-off criteria
Validate performance, stress, and corner scenarios such as congestion, backpressure, and error injection
Support emulation, FPGA prototyping, and post-silicon validation for Ethernet bring-up and debug

Cross-Functional Collaboration

Work closely with architecture, RTL, DFT, physical design, firmware, and software teams
Provide early verification input during architecture and micro-architecture definition, especially around standards compliance and performance assumptions
Collaborate with software teams on driver, firmware, and traffic validation

Mentorship & Process

Mentor and technically guide verification engineers across experience levels
Establish and enforce verification best practices and coding standards
Drive continuous improvements in verification flows, reuse, and productivity

Required Qualifications

Bachelor's or Master's degree in Electrical/Electronics Engineering or related field from reputed college
10+ years of experience in ASIC/SoC design verification
Strong hands-on expertise in SystemVerilog, UVM, and SVA
Strong understanding of Ethernet architecture and protocols (MAC, PCS, PHY interfaces)

Job Req Type: Experienced

Required Travel: Yes, 10% of the time

Shift Type: 1st Shift/Days

Principal Engineer, Design Verification