Fpga, Perl, Python, low power verification, Uvm, systemverilog, AMBA bus protocols, Baremetal processor environments, RTL development environments, verification platforms, transaction level modelling, test bench infrastructure, formal verification methods, emulation platforms

Fpga, Perl, Python, Emulation, RTL, Uvm, systemverilog

Spi, Uart, Usb, Verilog, I2c, Python, Perl, Can, safety simulators, GLS, vManager, Uvm, Specman, systemverilog, Xcelium, Cadence Tools, AI ML-based DV, VHDL, post-silicon verification, AHB, Formal JG applications, PAGLS

C, Fpga, Python, Perl, Uvm, RTL, AMBA bus protocols, systemverilog, Emulation platforms, Automation scripts, Transaction level modeling

Verilog, systemverilog, Rtl Design, Verification Manager, Test Bench