Physical Synthesis, Critical-path SPICE simulation, floorplanning, Timing analysis and closure, ECO implementation, Timing sign-off methodologies, Placement Routing, Physical design sign-off, Timing Constraints, RTL-to-GDSII physical implementation flow, Power optimization and convergence, Full-chip timing closure, PPA optimization

routing, floorplanning, physical optimization, LVS, physical ECO implementation, Cadence Innovus, congestion analysis, Physical Verification, sign-off, Placement, IR drop, Calibre, antenna checks, Physical Design, primetime, Synopsys ICC2, Timing Closure, ERC, DRC, Power Planning, RTL-to-GDSII, StarRC

power integrity , Chip-Package Co-Design, Physical Design, floorplanning, Bump Planning, Package Interface Design, Signal Integrity, EDA Tools, Package Design

Synopsys - ICC, Shell scripting, Tcl, Routing, Perl, Power grid analysis, Timing Closure, Place and Route tools, Antenna fixing, Floorplan, DRC-LVS closure, Signal Integrity, Placement, Physical Design, Cadence – Innovus Encounter

Tcl, coding constraints, low power designs

Perl Scripting, Tcl, PDN Methodology, Leakage Power, Dfm, Power Supply Management, Circuit Level Comprehension, PPA Targets, RTL to GDSII Implementation, High Frequency Design, Deep Sub-Micron Design, Sta, Signal Integrity, Power Gating, Physical Design, Timing Signoff, IC design, Multi-Vt Flow, Hardware

Tcl, C, Perl, Physical Verification, Timing Closure, floorplanning, Physical Design Implementation, Clock Planning, Placement and Routing

Tcl, PERL, Cadence Innovus, Tk

redhawk , Tcl, Python, Perl, Scripting Languages, Tempus, manufacturing sign-off, multi-clock domain handling, advanced nodes, ASIC SoC physical design, PrimeClouser, Cadence Innovus, Timing Analysis, Physical Verification, EDA Tools, DFT insertion, Calibre, EM IR analysis, primetime, Signal Integrity, low-power design, Voltus, reliability checks, power analysis