C, Debugging, Shell, Verilog, Tcl, System Verilog, Python, Perl, assertions, directed and constrained random methodologies, Uvm, Metric Driven Verification, formal verification methodologies

Verilog, Sata, Python, Perl, Usb, Uvm, constrained random verification, functional coverage, PCI Express, systemverilog, VMM, DV methodologies

arm architecture , C, Firmware, Soc Architecture, Verilog, Embedded Software, Python, Perl, Assembly, CPU architecture, Emulation, systemverilog, AMBA protocols, Simulation