Validation Testing, Data acquisition systems, Fmea, Dfmea, Simulation Design

synopsys primetime , Shell Scripting, Perl, Python, Tcl, Tempus, SI OCV AOCV POCV CDC, Setup Hold Analysis, StarRC, Timing Exceptions, Low-Power Timing Methodologies, Timing Convergence Techniques, Timing Signoff

reactor design , Automation, Solidworks, ANSYS, Heat Mass Transfer, Pressure Vessel Engineering, Production Planning, Autocad, Aspen Plus, reaction engineering, Mechanical Design, Lean Manufacturing, Aspen Hysys, CFD Analysis, Process Simulation

Pcie, Ethernet, protocol VIP integration, Mentor, Cadence, Uvm, systemverilog, advanced verification methodologies, Register modeling, PAM2, Avery, D2D, PAM4, Synopsys

System Verilog, Functional and Code Coverage Methodologies, Verification Closure Techniques, Uvm, Simulation and Regression Infrastructure

arc flash , power converters , power conditioning , Fpga, Dsp, Electrical Systems, Power Electronics, Grid-scale Power Electronics, Control Protection, Testing and Validation of Power Electronics Hardware, power quality, Power Electronics Hardware Simulation, Grid Code Compliance, Hardware in the Loop, Sensing Techniques, Semiconductors, AC and DC High Voltage and Medium Voltage Architectures, Circuit Design, Lab Scale Development, Packaging Techniques, Harmonics, Filters, Relays, Faults

Unix Shell Scripting, perl, Static Timing Analysis, Tcl, Innovus, EDA Tools, Digital Genus, EMIR, GAA technologies 2nm and below, Tempus, Voltus, ASIC digital implementation flows, FinFet nodes 7nm and below, Digital Design Flows