redhawk , Tcl, Perl, Python, SDC, Foundry PDKs, Implementation tool suite, EDA Tools, Power gating, Cadence, primetime, Tempus, Synopsys ICC2, CPF, Timing Analysis, TSMC, Physical Design, Synopsys, UPF, Cadence Innovus, Sta, Multi-voltage domains, Voltus, Signoff tools, Samsung, Low-power design techniques

Tcl, Routing, Perl, Netlist2GDSII Implementation, Power Integrity Analysis, primetime, Floor Planning, Physical Verification, Cadence Tools, Calibre, CTS, Innovus, Sta, ICC2, Physical Design Methodologies, Tk, Placement, PT-PX, sub-micron technology

Perl, Python, Tcl, Clock domain partitioning, Power integrity and power-aware physical implementation, Block and subsystem-level physical design flows, primetime, Fusion Compiler, Clock gating, Congestion analysis and resolution, Clock tree architecture, Tempus, Cadence Innovus, Skew management, Certus, Synopsys ICC2, Timing closure and constraint management

redhawk , Verilog, Fusion Compiler, Metal-only ECO Implementation, Timing Optimization, Signal Integrity Analysis, FLASH Process Technologies, Floorplan Exploration, Innovus, Calibre, low power design, GDSII Flow, VHDL, Physical Design, Starrcxt, Reliability Analysis, Clock Tree Synthesis

redhawk , Tcl, Verilog, PERL, Timing Optimization, Signal Integrity Analysis, Starrcxt, FLASH Process Technologies, Fusion Compiler, Calibre, Innovus, Power Grid Planning, VHDL, Physical Design, Clock Tree Synthesis, Reliability Analysis, Timing Closure