code coverage , Scsi, DDR, PERL, Pcie, Verilog, Sata, Python, Usb, Nvme, Tcl, LINT, Design Compiler, Digital ASIC Design methodology, cdc, primetime, Rtl Design, Synthesis, DisplayPort, assertions, Formality, Timing Analysis, systemverilog, Axi, AMBA, Eco, HDMI, CXL, AHB, Design Verification CAD tools, NCSim

Perl, Python, DFT knowledge, backend flows, on-chip clocking networks

C, Python, System Verilog, Tcl, Lab debug, FPGA debug, post-silicon validation, architectural modeling, Uvm, formal verification techniques, bit accurate C models